MEC3 - A PIPELINED ZERO SUPPRESSION AND TRIGGER MATCHING CHIP

The MEC3 chip is a demonstrator of the general purpose MEC architectur e. This architecture is intended for the digital front-end of detector channels where the detector signal is sampled at constant rate. In ad dition to simple storage during the first level trigger latency, data of interest are extracted by zero suppression and trigger matching. An event synchronized read-out interface takes care of merging event dat a from several channels. The three main ports (1: sampled data in, 2: trigger and 3: read-out), can run completely asynchronously. The synch ronization of the three ports inside the chip is performed at the even t level by the use of time tags and FIFOs. Zero suppression is perform ed by adaptive thresholding that takes baseline variations into accoun t. In addition a programmable FIR filter is available to process the s ignal before the pulse detection thresholding. Trigger matching is don e by a comparison between time tags of the extracted pulses and the tr igger decision. All functions ate implemented with a high level of pro grammability to accommodate different signal characteristics. Also spe cial handling of channel pile-up and clustering has been included. Ext ensive simulations at behavioral level have been performed to optimize the architecture and an ASIC has finally been implemented with standa rd cells in a 1.0 mu m CMOS process.