A FIRST-LEVEL CALORIMETER TRIGGER FOR THE ATLAS EXPERIMENT

In the RD27 collaboration we have carried out system studies on the im plementation of the first level calorimeter trigger processor system f or the ATLAS experiment to be mounted at the Large Hadron Collider (LH C) at CERN. These studies suggest that the full system can be containe d in six 18SU size crates which will process approximately 4000 electr omagnetic and 4000 hadronic trigger cells and provide the central trig ger processor (CTP) with signals from events with high-P-T electrons/p hotons, jets and missing-E(T). A demonstrator trigger system operated successfully with the RD3 and RD33 calorimeters at the full 40 MHz LHC bunch crossing (BC) rate [1]. The prototype application-specific inte grated circuits (ASICs) in this system each processed data from only a single trigger cell and its environment, which would lead to an extre mely large system for ATLAS. Using eight-bit parallel data even the us e of ASICs, processing multiple trigger cells would demand unacceptabl y large numbers of input pins and module connections. Initial studies of this I/O problem produced a solution based on asynchronous transmis sion of zero-suppressed and BC-tagged data on 160 Mbit/s serial links [2]. This approach appeared to be feasible but would have introduced a dditional latency of about 20 BCs. Further studies have led to the des ign of a fully-synchronous calorimeter trigger processor system using commercial high speed optical links. The links will terminate in multi -chip modules (MCMs) incorporating custom-designed integrated optics, and the trigger algorithms will be implemented in ASICs.