BEHAVIORAL SYNTHESIS OF AREA-EFFICIENT TESTABLE DESIGNS USING INTERACTION BETWEEN HARDWARE SHARING AND PARTIAL SCAN

We introduce BETS, a behavioral test synthesis system, for the synthes is of high-throughput, area-efficient testable designs. While hardware sharing is a powerful technique to achieve area efficiency, it may ad versely affect the testability of the synthesized design by introducin g new loops. Besides CDFG loops, hardware sharing introduces three oth er types of loops: assignment loops, sequential false loops, and regis ter files cliques. We provide a comprehensive analysis and a formal gr ammar characterization of the sources of loops in the data path during behavioral synthesis. Partial scan is a cost-effective technique for sequential circuit testing. Hardware sharing of scan registers can be used to minimize the number of scan registers required to synthesize d ata paths with minimal number of loops. The scan registers can be shar ed amongst several variables of the CDFG, to break not only the loops in the CDFG, but also the very loops introduced in the data path by ha rdware sharing. A new random walk based algorithm is proposed to break all CDFG loops using a minimal number of scan registers. The subseque nt scheduling and assignment phase avoids formation of loops in the da ta path by reusing the scan registers, while ensuring high resource ut ilization. The experimental results demonstrate the effectiveness of t he new technique to synthesize easily testable data paths, with nomina l hardware overhead, while maintaining the performance of the designs. The partial scan overhead incurred by the technique is significantly less than that of a gate-level partial scan approach.