A HIGHLY PARALLEL DSP ARCHITECTURE FOR IMAGE RECOGNITION

This paper presents a newly developed architecture for a highly parall el DSP suited for realtime image recognition. The programmable DSP was designed for a variety of image recognition systems, such as computer vision systems, character recognition systems and others. The DSP con sists of functional units suited for image recognition: a SIMD process ing core, a hierarchical bus, an Address Generation Unit, Data Memorie s, a DMA controller, a Link Unit, and a Control Unit. The high perform ance of 3.2GOPS is realized by the eight-parallel SIMD core with a opt imized pipeline structure for image recognition algorithms. The DSP su pports flexible data transfers including an extraction of local images from raster scanned image data, a table-loop-up, a data-broadcasting, and a data-shifting among processing units in the SIMD core, for effe ctive execution of various image processing algorithms. Hence, the DSP can process a 5 X 5 spatial filtering for 512 X 512 images within 13. 1 msec. Adopting the DSP to a Japanese character recognition system, t he speed of 924 characters/sec can be achieved for feature extractions and feature vectors matchings. The DSP can be integrated in a 14.5 X 14.5 mm(2) single-chip, using 0.5 mu m CMOS technology. In this paper, the key features of the architecture and the new techniques enabling efficient operation of the eight parallel processing units are describ ed. Estimation of the performance of the DSP is also presented.