BOTTLENECK IDENTIFICATION METHODOLOGY FOR PERFORMANCE-ORIENTED DESIGNOF SHARED-BUS MULTIPROCESSORS

A bottleneck identification methodology is proposed for the performanc e-oriented design of shared-bus multiprocessors, which are composed of several major subsystems (e.g. off-chip cache, bus, memory, I/O). A s ubsystem with the longest access time per instruction is the one that limits processor performance and creates a bottleneck to the system. T he methodology also facilitates further refined analysis on the access time of the bottleneck subsystem to help identify the causes of the b ottleneck. Example performance model of a particular shared-bus multip rocessor architecture with separate address bus and data bus is develo ped to illustrate the key idea of the bottleneck identification method ology. Accessing conflicts in subsystems and DMA transfers are also co nsidered in the model.