A NOVEL CIRCUIT TECHNOLOGY WITH SURROUNDING GATE TRANSISTORS (SGTS) FOR ULTRA-HIGH DENSITY DRAMS

This paper describes a novel circuit technology with Surrounding Gate Transistors (SGT's) for ultra high density DRAM's, In order to reduce the chip size drastically, an SGT is employed to all the transistors w ithin a chip, SGT's connected in series and a common source SGT have b een newly developed for the core circuit, such as a sense amplifier de signed by a tight design rule, Furthermore, to reduce the inherent cel l array noise caused by a relaxed open bit line (BL) architecture, a n oise killer circuit placed in the word line (WL) shunt region and a tw isted BL architecture within the sense amplifier region combined with a novel separation sensing scheme have been newly introduced, Using th e novel circuit technology, a 32.9% smaller chip size can be successfu lly achieved for a 64-Mb DRAM and 34.4% for a 1-Gb DRAM compared with a DRAM composed of the planar transistor without sacrificing the acces s time, power dissipation, and V-cc margin. Furthermore,the effectiven ess of this technology is verified by using the circuit simulation of the internal main nodes such as WL and BL.