A LOW-POWER CMOS TIME-TO-DIGITAL CONVERTER

Citation
E. Raisanenruotsalainen et al., A LOW-POWER CMOS TIME-TO-DIGITAL CONVERTER, IEEE journal of solid-state circuits, 30(9), 1995, pp. 984-990
Citations number
18
Categorie Soggetti
Engineering, Eletrical & Electronic
ISSN journal
00189200
Volume
30
Issue
9
Year of publication
1995
Pages
984 - 990
Database
ISI
SICI code
0018-9200(1995)30:9<984:ALCTC>2.0.ZU;2-L
Abstract
A time-to-digital converter, TDC, with 780 ps Isb and 10-mu s input ra nge has been integrated in a 1.2-mu m CMOS technology. The circuit is based on the interpolation time interval measurement principle and con tains an amplitude regulated crystal oscillator, a counter, two pulse- shrinking delay lines, and a delay-locked loop for stabilization of th e delay. The TDC is designed for a portable, low-power laser range-fin ding device. The supply voltage is 5 +/- 0.5 V, and the operating temp erature range is -40 to + 60 degrees C. Single-shot accuracy is 3 ns a nd accuracy after averaging is +/- 120 ps with input time intervals 5- 500 ns. In the total input range of 10 mu s, the final accuracy after averaging is +/- 200 ps, Current consumption is 3 mA, and the chip siz e is 2.9 mm 2.5 mm.