TEST PATTERN GENERATION FOR CROSSTALK FAULTS CONSIDERING THE GATE DELAY

Citation
N. Itazaki et al., TEST PATTERN GENERATION FOR CROSSTALK FAULTS CONSIDERING THE GATE DELAY, Systems and computers in Japan, 26(7), 1995, pp. 24-33
Citations number
13
Categorie Soggetti
Computer Science Hardware & Architecture","Computer Science Information Systems","Computer Science Theory & Methods
ISSN journal
08821666
Volume
26
Issue
7
Year of publication
1995
Pages
24 - 33
Database
ISI
SICI code
0882-1666(1995)26:7<24:TPGFCF>2.0.ZU;2-2
Abstract
This paper presents a new method of test pattern generation for detect ing crosstalk faults. In general, to detect crosstalk faults, two succ essive test vectors are needed for exciting and propagating the crosst alk fault. A special signal corresponding to the two successive vector s is designed to simplify the test pattern generation algorithm and it s implementation. By taking into consideration gate delay, more accura te test pattern generation can be expected. The algorithm was implemen ted in a C++ program, and applied to a few benchmark circuits. The exp eriments show that coverage for large-scale integrated circuits is at least 70 percent, and for small-scale integrated circuits up to 90 per cent.