10GBIT S CLOCK RECOVERY CIRCUIT USING TEMPERATURE COMPENSATED DIELECTRIC RESONATOR FILTER/

A clock recovery circuit using a dielectric resonator filter (DRF) for 10Gbit/s data regeneration is presented, where a temperature compensa tion technique was for the first time employed to keep the relative ph ase between the input data and clock to the decision circuit as consta nt as possible. The experimental results showed an output clock phase variation of <+/-6deg over the operating temperature range from 0 - 75 degrees C and the measured maximum RMS jitters of <2ps with the reson ance detunings of up to +/-10MHz.