PERFORMANCE OF CMOS TERNARY FULL ADDER AT LIQUID-NITROGEN TEMPERATURE

We have designed, implemented and studied the performance at liquid ni trogen temperature (77 K) of a CMOS ternary full adder and its buildin g blocks, the simple ternary inverter (STI), positive ternary inverter (PTI) and negative ternary inverter (NTI), and compared the correspon ding performance at room temperature (300 K). The ternary full adder h as been fabricated in 2 mu m, n-well CMOS through MOSIS. In a ternary full adder, the basic building blocks, the PTI and NTI, have been deve loped using combinations of a CMOS inverter and transmission gate(s). There is close agreement between the simulated and measured voltage tr ansfer characteristics and noise margins of ternary-valued devices. Th e measured transient times for the NTI, PTI and ternary full adder at 77 K show an improvement by a factor of approximate to 1.5-2.5 over th e corresponding values at 300 K. The present design does not use linea r resistors and depletion-mode MOSFETs to implement the ternary full a dder and its building blocks, and is fully compatible with current CMO S technology.