PERFORMANCE OF MVTL LOGIC AT MULTI-GHZ FREQUENCIES

Demonstrating superconductive logic circuits at high speeds is crucial in gaining acceptance by potential users. We are taking an integrated approach toward demonstrating the potential of such circuits. Issues that are addressed include the effects that layout have upon a circuit and gate (particularly in scaling down the size of gates to increase density), testing limitations, designing for minimum crosstalk and gro und ripple, and fundamental limitations to gate performance. In this p aper, we report our progress in resolving and understanding these issu es. Circuits such as shift registers were used to understand the influ ence of layout on performance, circuits such as gate chains and puncht hrough detectors to explore fundamental gate limitations. We also repo rt on signal processing circuits of several hundred gates tested at cl ock frequencies up to several hundred MHz and the relationship between these results and the fundamental gate performances.