RSFQ ARITHMETIC BLOCKS FOR DSP APPLICATIONS

We have designed a Rapid Single-Flux-Quantum (RSFQ) bit-serial real-ti me pipeline multiplier for digital signal processing (DSP) application s. A single-bit module of this multiplier consists of 96 Josephson jun ctions and uses a B-flip-flop-based carry-save adder (CSA). For HYPRES ' standard 1-kA/cm(2) Nb process with 3.5 mu m-diameter Josephson junc tions the module occupies an area of 350 x 600 mu m(2). Simulations sh ow that the circuit should dissipate 28 mu W of power at 2.6 mV dc sup ply voltage and operate at frequencies of up to 25 GHz. We have succes sfully tested all cells of tire module and verified correct operation of a simplified version of the module at low frequencies. According to numerical simulations, tire speed of the multiplier is limited by the CSA. In order to overcome this bottleneck we have developed a concept of a fast carry-save pipeline adder based on XOR gates which uses an RSFQ-specific algorithm for carry bit calculation.