ON-CHIP PICOSECOND DELAY MEASUREMENT OF RSFQ DIGITAL LOGIC GATES

Because RSFQ circuits are intended to operate at multi-GHz frequencies , a logical,requirement for developing the technology is a method of a ccurately measuring the picosecond delays associated with individual l ogic circuits. A technique has been developed for on-chip measurements of such RSFQ gate delays. The central element In this scheme is a rac e between a path of calibrated variable delay and a path of unknown de lay, Modification of the canonical RSFQ RS flipflop circuit yields a m ultiple state destructive readout cell (MDRO), in which one can config ure the number of flux quanta to be stored. This circuit has been expe rimentally verified for groups of two flux quanta. Used in concert wit h the confluence buffer, this scheme can provide the RSPQ designer wit h sub-picosecond pulse arrival delay information crucial for higher or der circuit simulation. A detailed experimental process is presented f rom which this timing information can be extracted using basic low-spe ed measurement techniques.