ADDER-ACCUMULATOR CELLS IN RSFQ LOGIC

We are in the process of designing a Finite Impulse Response (FIR) fil ter for use in a Digital Signal Processing (DSP) system based entirely on Rapid Single Flux Quantum (RSFQ) logic. One aspect of this project involves the development of the arithmetic unit of the filter, in thi s case an adder-accumulator multiplier. This article describes two cel ls which can perform the function of accumulated binary addition in th e adder-accumulator multiplier. We have fabricated both cells and test ed them at low speed.