We have systematically studied designs for Modified Variable Threshold
Logic Gates (MVTL) in NbN within the framework of factorial analysis.
Our goal is to attain optimized margin and fanout for 10 K operation,
parasitic inductances, associated with crowding at junction vias, wer
e measured and are found to affect the operating margin. We report the
progression of designs, margin measurements and yield data for our 10
K circuits.