A CLOCK DISTRIBUTION SCHEME FOR LARGE RSFQ CIRCUITS

A primary issue in maximizing the performance of large scale synchrono us digital systems is the clock distribution scheme. We present a nove l clocking scheme, developed specifically for RSFQ logic, which is bas ed on the concurrent flow of the clock and data signals. The scheme pe rmits the circuit throughput to be independent of inter-cell connectio n delays and significantly reduces the dependence of the throughput on the clock-to-output delay of the cells. Concurrent flow clocking is p articularly well suited for structured architectures. The simulated ma ximum clock frequency of an RSFQ decimation digital filter currently u nder development at the University of Rochester can be as much as seve n times higher using concurrent-flow clocking rather than conventional (counterflow) clocking. This advantage, however, is reduced to a fact or of two due to fabrication process parameter variations in present d ay superconductive technologies.