SELF-TIMED DIVIDER USING THE REDUNDANT SIGNED-DIGIT NUMBER SYSTEM

A divider structure that combines a novel self-timed ring structure an d a carry-propagation-free division algorithm is proposed. The self-ti med ring structure enables the divider to compute at a speed comparabl e to that of previously designed dividers but with less silicon area. By exploiting the carry-propagation-free division algorithm, even bett er performance can be achieved. A 54-bit divider employing the propose d structure and a non-overlapped scheme has been implemented in 1.2 mu m CMOS technology, obtaining a speed of 193 ns per worst-case divisio n on 4.3 mm(2) of silicon area.