CHARGE CENTROID AND ORIGIN OF GENERATED AND INTRINSIC BULK DEFECTS AT293 AND 100 K IN INSULATED GATE FIELD-EFFECT TRANSISTORS

Citation
Hs. Kim et al., CHARGE CENTROID AND ORIGIN OF GENERATED AND INTRINSIC BULK DEFECTS AT293 AND 100 K IN INSULATED GATE FIELD-EFFECT TRANSISTORS, Journal of applied physics, 81(3), 1997, pp. 1566-1574
Citations number
28
Categorie Soggetti
Physics, Applied
Journal title
ISSN journal
00218979
Volume
81
Issue
3
Year of publication
1997
Pages
1566 - 1574
Database
ISI
SICI code
0021-8979(1997)81:3<1566:CCAOOG>2.0.ZU;2-K
Abstract
Intrinsic and generated bulk defects in the gate insulator of silicon insulated gate field effect transistors were examined using a continuo us forward-bias pulsed injection technique to inject up to 10(17) e/cm (2) at 293 and 100 K, for insulator thicknesses ranging between 5.4 an d 50.5 nm. The amount of trapping observed at 100 K was about 30 times greater than that at 293 K. The additional trapping at the reduced te mperature was determined to come from two sources. One is trapping by existing shallow bulk defects, and the other is an increase in the den sity of generated bulk defects. The defect generation process is thoug ht to be related to the neutral hole trap becoming unstable during inj ection, acting as an electron trap. This instability appears to be enh anced as the temperature is reduced to 100 K by a ''freeze out'' effec t, or by higher energy carriers that result from a reduction in the th ermal scattering. The defect generation rate follows a power law, much like a chemical rate equation, i.e., the rate of defect generation is dependent on the injection current density, much like a chemical reac tion is dependent on pressure of the reactive species. The charge cent roid of the generated defects, measured from the substrate/oxide inter face, was determined at both temperatures and the centroid of the shal low electron traps was determined at 100 K. These were found to be in the range of 6-8 nm at 100 K and 10-16 nm at 293 K. Also, a defect fre e, or tunneling, region of 2-4 nm extent was determined to exist at ea ch interface. This implies that when the oxide thickness decreases to about 4-8 nm, no threshold voltage shift should result from carrier in jection at room, or low temperature, and in fact this behavior was obs erved in these devices (at least up to 10(17) e/cm(2) injected). It wa s found that the shallow traps can be rapidly depopulated by subjectin g the devices to ordinary white light during normal device use, pointi ng to a possible method to improve device reliability at 100 K. (C) 19 97 American Institute of Physics.