AN ADVANCED DIAGNOSTIC METHOD FOR DELAY FAULTS IN COMBINATION FAULTY CIRCUITS

Due to physical defects or process variations, a logic circuit may fai l to operate at the desired clock speed. So, verifying the timing beha vior of digital circuits is always necessary, and needs to test for de lay faults. When a delay fault has been detected, a specific diagnosti c method is required to locate the site of the fault in the circuit. S o, a reliable method for delay fault diagnosis is proposed in this pap er. Firstly, we present the basic diagnostic method for delay faults, which is based on multivalued simulation and critical path tracing. Ne xt, heuristics are given that decrease the number of critical paths an d improve diagnosis results. In the second part of this paper, we prov ide an approximate method to refine the results obtained with the basi c diagnostic process. We compute the detection threshold of the potent ial delay faults, and use statistical studies to classify the faults f rom the most likely to be the cause of failure to the less likely. Fin ally, results obtained with ISCAS'85 circuits are presented to show th e effectiveness of the method.