A HIGH-FIDELITY DECIMATOR CHIP FOR THE MEASUREMENT OF SIGMA-DELTA MODULATOR PERFORMANCE

This paper reports on results from the algorithmic design and simulati on of a two-path polyphase decimation filter with 24-bit accuracy over the frequency range from de to 15.2 kHz, The filter is suited for ver y high precision data conversion and measurement applications. The dev ice reported in this paper has been designed for use with a fourth-ord er, single-loop, Sigma Delta modulator running at 4096 kHz. Results of floating and fixed-point simulations, architectural design, comparati ve bit-level simulations and silicon implementation of the decimator a re also reported, together with a sample baseband measurement of a fou rth-order modulator.