RESIDUE SYSTOLIC IMPLEMENTATIONS FOR NEURAL NETWORKS

In this work we propose two techniques for improving VLSI implementati ons for artificial neural networks (ANNs). By making use of two kinds of processing elements (PEs), one dedicated to the basic operations (a ddition and multiplication) and another to evaluate the activation fun ction, the total time and cost for the VLSI array implementation of AN Ns can be decreased by a factor of two compared with previous work. Ta king the advantage of residue number system, the efficiency of each PE can be further increased. Two RNS-based array processor designs are p roposed. The first is built by look-up tables, and the second is const ructed by binary adders accomplished by the mixed-radix conversion (MR C), such that the hardwares are simple and high speed operations are o btained. The proposed techniques are general enough to be extended to cover other forms of loading and learning algorithms.