A FAULT SIMULATION METHOD FOR CROSSTALK FAULTS IN SYNCHRONOUS SEQUENTIAL-CIRCUITS

With the scale-down of VLSI chip size and the reduction of switching t ime of logic gates, crosstalk faults become an important problem in te sting of VLSI. For synchronous sequential circuits, the crosstalk puls es on data lines will be considered to be harmless, because they can b e invalidated by a clocking phase. However, crosstalk pulses generated on clock lints or reset lines will cause an erroneous operation. In t his work. we have analyzed a crosstalk fault scheme. and developed a f ault simulator based on the scheme. Throughout this work, we considere d the crosstalk fault as unexpected strong capacitive coupling between one data line and one clock line. Since we must consider timing in ad dition to a Logic value, the unit delay model is used in our fault sim ulation. Our experiments on some benchmark circuits show that fault ac tivation rates and fault detection rates vary widely depending on circ uit characteristics. Fault detection rates of up to 80% are obtained f rom our simulation with test vectors generated at random.