USING CONDITIONAL EXECUTION TO EXPLOIT INSTRUCTION LEVEL CONCURRENCY

Multiple-instruction-issue processors seek to improve performance over scalar RISC processors by providing multiple pipelined functional uni ts in order to fetch, decode and execute several instructions per cycl e, The process of identifying instructions which can be executed in pa rallel and distributing them between the available functional units is referred to as instruction scheduling. This paper describes a simple compile-time scheduling technique, called conditional compaction, whic h uses the concept of conditional execution to move instructions acros s basic block boundaries. It then presents the results of an investiga tion into the performance of the scheduling technique using C benchmar k programs scheduled for machines with different functional unit confi gurations. This paper represents the culmination of our investigation into how much performance improvement can be obtained using conditiona l execution as the sole scheduling technique.