ACTIVE TIMING MULTILEVEL FAULT-SIMULATION WITH SWITCH-LEVEL ACCURACY

This paper describes SATISFAULT, a new hierarchical multilevel fault s imulator with switch-level fault models and switch-level accuracy. SAT ISFAULT's intelligent scheduling mechanism switches between the abstra ction levels to force simulation at the highest, thus fastest, possibl e level of abstraction without losing switch-level accuracy, The simul ation algorithm is based on single fault-propagation for active faults , It deals with multiple abstraction levels and supports the inertial delay model, As a result, even large circuits may be fault-simulated a ccurately with all faults injected at the switch-level, Complete fault -simulation of all transistors stuck-on and stuck-open of circuits up to 105 000 transistors including faults inside flip-flops is possible in reasonable time. In addition, SATISFAULT is also capable to simulat e bridging faults for IddQ detectability.