A PARTITION AND RESYNTHESIS APPROACH TO TESTABLE DESIGN OF LARGE CIRCUITS

We present a new area-efficient procedure for embedding test function into the gate-level implementation of a sequential circuit. First, we develop a test machine embedding technique for a given gate-level impl ementation of a finite state machine. The test machine states are mapp ed onto the states of the given circuit such that a minimum number of new state variable dependencies are introduced. The composite function is optimized, Experimental results show that our method yields testab le machine implementations that have lower area than the corresponding full scan designs. The test generation complexity for our machine imp lementation is the same as that for a full scan design, To apply the m ethod to large gate-level designs, we partition the circuit into inter connected finite-state machines, Each component state machine can be s pecified either as its gate-level implementation or as the extracted s tate diagram, We incorporate test functions into each component finite state machine such that the entire interconnection of the augmented c omponents has the same testability properties as the product machine w ith a single test function, ISCAS '89 benchmark circuits are partition ed into component finite state machines using a new testability-direct ed partitioning algorithm. Again, our embedding procedure results;in t estable circuits that have lower area than the corresponding full scan designs.