A new performance model of the memory hierarchy is first introduced, w
hich describes all possible senarios for the calculation process, incl
uding the important case when the cache memory is by-passed. A detaile
d study of each scenario is then given along with the derivation of co
rresponding formulae. In these formulae the cache load time associated
with the penalty which must be paid to transfer data between the main
memory and the cache is also taken into account. A two-parameter line
ar model for performance characterisation of cache memory effect is in
troduced. The double-performance parameter, n(2), is defined to descri
be the performance degradation for problem sizes that do not fit into
the cache memory. This parameter determines the problem size required
to preserve twice the asymptotic performance. A non-linear timing mode
l is described as the most complex case of cache memory characterisati
on. Excellent agreement is shown between the estimated performance fig
ures and several benchmark measurements on iPSC/860.