CHARACTERIZATION BASED BOTTLENECK ANALYSIS OF PARALLEL SYSTEMS

Bottleneck analysis plays an important role in the early design of par allel computers and programs. In this paper a methodology for bottlene ck analysis based on an instruction level characterisation technique i s presented. The methodology is based on the assumption that a bottlen eck is caused by the slowest component of a computing system, These co mponents are: memory (internal, external), processor (CPU, FPU), commu nication and I/O. Three metrics were used to identify bottlenecks in t he system components. These are the B-ratio, the communication-computa tion ratio and the memory-processing ratio. These ratios are dimension less and indicate the presence of a bottleneck when their values excee d unity. The methodology is illustrated and validated using a communic ation intensive linear solver algorithm (Gauss-Jordan elimination) whi ch was implemented on a mesh connected distributed memory parallel com puter (128 T800 Parsytec SuperCluster).