LOW-POWER BUILDING-BLOCK FOR ARTIFICIAL NEURAL NETWORKS

The authors propose and analyse a low-power CMOS building block for ar tificial neural networks (ANNs) that can function either as a synapse or a neuron. The design is based on the current-mode approach and uses the square-law characteristics of a MOS transistor working in saturat ion. The new building block uses I-V converters, a current-mirror and a +/- 1 V power supply to achieve superior performance, Modularity, ea se of interconnectivity, expandability and reconfigurability are the a dvantages of this building block.