THRESHOLD VOLTAGE MINIMUM GATE LENGTH TRADE-OFF IN BURIED-CHANNEL PMOS DEVICES FOR SCALED SUPPLY VOLTAGE CMOS TECHNOLOGIES

In this letter the trade-off between threshold voltage (V-th) and the minimum gate length (L(min)) is discussed for optimizing the performan ce of buried channel PMOS transistors for low voltage/low power high-s peed digital CMOS circuits. In a low supply voltage CMOS technology it is desirable to scale V-th and L(min) for improved circuit performanc e. However, these two parameters cannot be scaled independently due to the channel punch-through effect. Statistical process/device modeling , split lot experiments, circuit simulations, and measurements are per formed to optimize the PMOS transistor current drive and CMOS circuit speed. We show that trading PMOS transistor V-th for a smaller L(min) results in faster circuits for low supply voltage (3.3 to 1.8 V) n(+)- polysilicon gate CMOS technology, Circuit simulation and measurements are performed in this study. Approximate empirical expressions are giv en for the optimum buried channel PMOS transistor V-th for minimizing CMOS circuit speed for cases involving: (1) constant capacitive load a nd (2) load capacitance proportional to MOS gate capacitance, The resu lts of the numerical exercise are applied to the centering of device p arameters of a 0.5 mu m 3.3 V CMOS technology that (a) matches the spe ed of our 0.5 mu m 5 V CMOS technology, and (b) achieves good performa nce down to 1.8 V power supply [1]. For this process the optimum PMOS transistor V-th (absolute value) is approximately 0.85-0.90 V.