A NOTE ON COMPILING FORTRAN LOOP KERNELS ONTO A DATA-FLOW ARCHITECTURE

Currently, dataflow architectures are programmed using applicative lan guages to ease the task of deriving the dataflow graph during compilat ion. We summarise our experience gained in prototyping a FORTRAN neste d loop kernel compiler for a pipeline-ring dataflow architecture. We p resent the status of the current implementation and future directions which the development of the compiler will take. Current evidence sugg ests that it is possible to efficiently compile FORTRAN nested loop ke rnels directly onto dataflow architectures without the need for additi onal run-time support mechanisms. We present a scheme for deriving the dataflow graph from the analysis of ''carried'' array variable subscr ipt expressions, and a scheme to map the actors in the dataflow graph onto a pipeline-ring of Field Programmable Gate Array (FPGA) devices.