TOTEM - A HIGHLY PARALLEL CHIP FOR TRIGGERING APPLICATIONS WITH INDUCTIVE LEARNING BASED ON THE REACTIVE TABU SEARCH

The training of a Multi-Layer Perceptron (MLP) classifier is considere d as a Combinatorial Optimization task and solved using the Reactive T abu Search (RTS) method. RTS needs only forward passes (no derivatives ) and does not require high precision network parameters. TOTEM, a spe cial-purpose VLSI chip, was developed to take advantage of the limited memory and processing requirements of RTS: the final system effects a very close match between hardware and training algorithm. The RTS alg orithm and the design of TOTEM are discussed, together with the operat ional characteristics of the VLSI chip and some preliminary training a nd generalization tests on triggering tasks.