LOW-POWER DISSIPATION GAAS DCFL 2.5GBPS 16-BIT MULTIPLEXER DEMULTIPLEXER LSIS/

In order to establish design and measurement technologies for an LSI t hat features high speed operation and low power dissipation, GaAs 2.5 Gbps 16 bit MUX/DEMUX LSIs have been successfully developed. DCFL is e mployed as a basic gate in order to reduce the power dissipation. For the purpose of achieving stable operation against the transistor param eter deviation, a timing design called clock tracking is employed. Mor eover, to ensure accurate performance measurement, a new measurement s ystem is introduced. The measurement system consists of an error rate detector (ERD), a pulse pattern generator (PPG) and a high speed teste r (HST). The performances tested by the measurement system show the po wer consumptions of MUX and DEMUX LSIs are 1.35 W and 0.95 W. Input ph ase margin of DEMUX LSI is 290 degrees at 2.5 Gbps operation. The tech nologies obtained through development of these MUX/DEMUX LSIs are appl icable to other high speed and low power LSIs.