A 15-GBIT S SI-BIPOLAR GATE ARRAY

We have developed a 15-Gbit/s 96-gate Si-bipolar gate array using 0.5- mu m Si-bipolar technology, a sophisticated internal cell design, an I /O buffer design suitable for high-speed operation and high-frequency package technology. The decision circuit and 4:1 multiplexer fabricate d on the gate array operate up to 15-Gbit/s and above 10-Gbit/s respec tively. The data input sensitivity and the phase margin of the decisio n circuit are 53 mV(pp) and 288 degrees at 10-Gbit/s operation. This g ate array promises to be useful in shortening the development period a nd lowering cost of 10-Gbit/s class IC's.