DESIGN OF A NOVEL MOS V-T EXTRACTOR CIRCUIT

This paper describes a novel input-free MOS V-T extractor circuit. The circuit consists of a bias voltage block and a novel V-T extractor bl ock. The proposed V-T extractor block has the advantages of the ground -referenced output, low influences of the nonideality, few numbers of transistors and no influence of the PMOS process. The PSpice simulatio ns show the supply voltage range and the bias voltage range of the pro posed circuit are wider than those of Johnson's or Wang's.