AN EFFICIENT BIT-SERIAL FIR FILTER ARCHITECTURE

A new bit-serial architecture for implementation of high order FIR fil ters is introduced, as well as example FPGA and CMOS realizations. Thi s structure exploits the simplicity of coefficients that consist of tw o power-of-two terms to yield efficient implementations. Quantization effects are discussed and a simple block scaling method for reducing r ounding and truncation noise in high order filters is also presented.