An 800-MHz monolithic mixed-signal serrodyne modulator IC has been dev
eloped in a GaAs/AlGaAs HBT HI(2)L process optimized for digital appli
cations, This 3 x 2.8 mm,, 2000+ transistor chip consists of a 7-b pha
se accumulator driving a vector modulator, implemented as a pair of ba
lanced mixers, 5-b switched-attenuators, buffer amplifiers, and contro
l circuits, The balanced mixer's LO leakage and 3-1 products are typic
ally 25 dB below the carrier at the nominal operating point, with all
other products better than -50 dBc, Over a 32-dB control range, the 5-
b switched attenuator typically achieves worst-case amplitude acid pha
se errors of 1.5 dB and 1.5 degrees, respectively, from 50-250 MHz, DC
-level variations versus attenuator-state limit the spurious response
of an 800-MHz Composite DDS based on this serrodyne modulator to -20 d
Bc, Post-fabrication modeling indicates that a 5 degrees C thermal gra
dient across the IC may be responsible for this undesired dc-level var
iation, This first generation chip consumes 2.5 W of dc power and cloc
ks to speeds in excess of 925 MHz.