POWER RAIL LOGIC - A LOW-POWER LOGIC STYLE FOR DIGITAL GAAS CIRCUITS

Authors
CHANDNA A BROWN RB PUTTI D KIBLER CD
Citation
A. Chandna et al., POWER RAIL LOGIC - A LOW-POWER LOGIC STYLE FOR DIGITAL GAAS CIRCUITS, IEEE journal of solid-state circuits, 30(10), 1995, pp. 1096-1100
Citations number
4
Categorie Soggetti
Engineering, Eletrical & Electronic
Journal title
IEEE journal of solid-state circuits → ACNP
ISSN journal
00189200
Volume
30
Issue
10
Year of publication
1995
Pages
1096 - 1100
Database
ISI
SICI code
0018-9200(1995)30:10<1096:PRL-AL>2.0.ZU;2-A
Abstract
This paper describes a new logic style called Power Rail Logic (PRL), which is compatible with direct-coupled FET logic (DCFL) circuits, Mul tiplexors, latches, flip-flops, and exclusive-OR gates can be built us ing this logic style, Compared to DCFL, PRL uses fewer transistors, ha s larger noise margins, and up to 40% tower power-delay products, A te st chip containing 32-b barrel shifters designed in DCFL acid in PRL w as successfully fabricated and tested, Test results are given for bath circuits.