0.9-V DSP BLOCKS - A 15-NS 4-K SRAM AND A 45-NS 16-B MULTIPLY ACCUMULATOR

4-k SRAM and 16-b multiply/accumulate DSP blocks have been designed an d fabricated in Complementary heterostructure GaAs. Both circuits oper ate from 1.5 V to below 0.9 V. The SRAM uses 28272 transistors in an a rea of 2.44 mm(2), Cell size is 278 mu m(2) at 1.0-mu m gate length. M easured results show an access delay of 5.3 ns at 1.5 V and 15.0 ns at 0.9 V. At 0.9 V, the power dissipated is 0.36 mW, The CGaAs multiplie r uses a 16-b modified Booth architecture with a 3-way 40-b accumulato r. The multiplier uses 11200 transistors in an area of 1.23 mm(2), Mea sured delay is 19.0 ns at 1.5 V and 44.7 ns at 0.9 V, At 0.9 V, curren t is less than 0.4 mA.