THE EFFECT OF MANUFACTURING AND DESIGN PROCESS VARIABILITIES ON THE FATIGUE LIFE OF THE HIGH-DENSITY INTERCONNECT VIAS

Citation
Ao. Ogunjimi et al., THE EFFECT OF MANUFACTURING AND DESIGN PROCESS VARIABILITIES ON THE FATIGUE LIFE OF THE HIGH-DENSITY INTERCONNECT VIAS, JOURNAL OF ELECTRONICS MANUFACTURING, 5(2), 1995, pp. 111-119
Citations number
10
Categorie Soggetti
Engineering, Eletrical & Electronic","Engineering, Manufacturing
ISSN journal
09603131
Volume
5
Issue
2
Year of publication
1995
Pages
111 - 119
Database
ISI
SICI code
0960-3131(1995)5:2<111:TEOMAD>2.0.ZU;2-L
Abstract
Via fatigue failure has been identified(4) as a potential failure mech anism in high density interconnects. This failure mechanism is directl y influenced by the stress-strain level at the potential points of fai lure in the structure and the ductility of the via material. This pape r looks at the effect of some manufacturing and design process variabl es on the fatigue life of the vias. The key variables are the trace or conductor thickness (metallization thickness), the layer or layers of the dielectric around the trace and in the via, the via geometry, wal l slope, the ductility coefficient of the conductor material and the s train concentration factor. The metallization thickness is found to ha ve the most dramatic effect on the fatigue life of the via compared to the other design variables. Good via ductility and strain concentrati on factors improve the fatigue life drastically.