USE OF MINIMUM-ADDER MULTIPLIER BLOCKS IN FIR DIGITAL-FILTERS

The computational complexity of VLSI digital filters using fixed point binary multiplier coefficients is normally dominated by the number of adders used in the implementation of the multipliers. It has been sho wn that using multiplier blocks to exploit redundancy across the coeff icients results in significant reductions in complexity over methods u sing canonic signed-digit (CSD) representation, which in turn are less complex than standard binary representation. Three new algorithms for the design of multiplier blocks are described: an efficient modificat ion to an existing algorithm, a new algorithm giving better results, a nd a hybrid of these two which trades off performance against computat ion time. Significant savings in filter implementation cost over exist ing techniques result in all three cases. For a given wordlength, it w as found that a threshold set size exists above which the multiplier b lock is extremely likely to be optimal. In this region, design computa tion time is substantially reduced.