A PARALLEL ARCHITECTURE FOR THE COMPUTATION OF UNIFORM RATIONAL B-SPLINE PATCHES

Several hardware implementations of lines, circles, and polygons have been reported in the literature. However, the hardware implementation of parametric curves and patches has started to receive similar attent ion only recently. In this paper, a unified VLSI architecture for gene rating rational and nonrational uniform B-spline curves and patches is presented along with its performance evaluation. It is shown that thi s architecture overcomes several limitations of earlier hardware solut ions. (C) 1995 Academic Press, Inc.