RECENT DEVELOPMENTS IN ELECTRICAL LINEWIDTH AND OVERLAY METROLOGY FORINTEGRATED-CIRCUIT FABRICATION PROCESSES

Electrical linewidth measurements have been extracted from test struct ures replicated in planar films of monocrystalline silicon that were e lectrically insulated from the bulk-silicon substrate by a layer of si licon dioxide formed by separation by the implantation of oxygen (SIMO X) processing. Appropriate selection of the surface orientation of the starting material, the design and orientation of the structure's feat ures, and patterning by a lattice-plane selective etch provide feature s with planar, atomically smooth sidewalls and rectangular cross secti ons. The primary motivation for this approach is to attempt to overcom e the serious challenge posed by methods divergence to the certificati on of linewidth reference-materials for critical-dimension (CD) instru ment calibration and related tasks. To enhance the physical robustness of reference features with deep submicrometer linewidths, the new tes t structure embodies short reference-segment lengths and arbitrarily w ide voltage taps. Facilities for reconciliation of measurements extrac ted from the same feature by all normally practiced techniques are als o implemented. In overlay metrology, electrical inspection of two type s of hybrid overlay targets allows pixel calibration of, and shift ext raction from, the overlay instruments. The overall strategic focus of this research is to resolve methods-divergence issues and possibly to develop universal deep-submicrometer linewidth reference materials for CD instruments and techniques for instrument- and process-specific sh ift extraction for optical overlay metrology.