PIPELINE INTERLEAVING DESIGN FOR FIR, IIR, AND FFT ARRAY PROCESSORS

In this paper, a floating point multiply-and-accumulate (FMAC) process or capable of running the FIR, IIR, and FFT algorithms is proposed. Th is processor executes many independent FMAC operations circularly with out causing any hazard. The algorithmic processing is decomposed into independent subprocesses, each of which executes a FMAC group and all of the subprocesses are activated in turn. The projection method of VL SI array processors is used to map the data flow of FIR, IIR, and FFT into subprocesses so that the algorithms can be successfully executed by the processor in the way of pipeline interleaving. Because of the 1 00% utilization of pipeline, a very good performance is achieved.