A SCALABLE DESIGN FOR VLSI DICTIONARY MACHINES

Most of the proposed VLSI dictionary machines appearing in the literat ure were designed to fit in one chip only. If the number of acquired e lements is larger than that of VLSI cells, another chip has to be desi gned and manufactured to take a larger dictionary into account. In thi s paper, we propose a new design for dictionary machines that assemble s blocks of standard existing dictionary machines. Our machine is as e fficient as the best machines described in the literature, with the en ormous advantage of scaling up quite easily, with no degradation of it s performance, by simply adding more and more standard blocks.