ARCHITECTURE AND PROGRAMMING OF 2 GENERATIONS VIDEO SIGNAL PROCESSORS

Programmable video signal processor ICs (VSPs) and dedicated programmi ng tools have been developed for the real-time processing of digital v ideo signals. A large number of applications have been developed with boards containing several of these processors. Currently two implement ations of the general architecture exist: VSP1 and VSP2. A single VSP chip contains several arithmetic and logic elements (ALEs) and memory elements. A complete switch matrix implements the unconstrained commun ication between all elements in a single cycle. The programming of the se processors is carried out with signal flow graphs. These signal flo w graphs can conveniently express multi-rate algorithms. These algorit hms are then mapped onto a network of processors. Mapping is decompose d into delay management, partitioning and scheduling. The solution str ategies for the partitioning problem and the scheduling problem are il lustrated. Applications with these processors have been made for a num ber of industrially relevant video algorithms, including the complete processing of next generation fully digital studio TV cameras and seve ral image improvement algorithms in medical applications. Results of t he mapping are presented for a number of algorithms in the field of TV processing.