MAPPING REAL-TIME MOTION ESTIMATION TYPE ALGORITHMS TO MEMORY EFFICIENT, PROGRAMMABLE MULTIPROCESSOR ARCHITECTURES

In this paper, an architectural template is presented, which is able t o execute the full search motion estimation algorithm or other similar video or image processing algorithms in real time. The architecture i s based on a set of programmable video signal processors (VSP's). It i s also possible to integrate the processor cores and their local memor ies on a (set of) chip(s). Due to the programmability, the system is v ery flexible and can be used for emulation of other similar block-orie nted local-neighborhood algorithms. The architecture can be easily div ided into several partitions, without data-exchange between partitions . Special attention is paid to memory size and transfer optimization, which are dominant factors for both area and power cost. The trade-off s and techniques used to arrive at these solutions are explained in de tail. It is shown that careful optimizations can lead to large savings in memory size (up to 66%) and bandwidth requirements (up to a factor of 4) compared to a straightforward solution.