A STUDY FOR TESTABILITY OF REDUNDANT FAULTS IN COMBINATIONAL-CIRCUITSUSING DELAY EFFECTS

Some undetectable stuck-at faults called the redundant faults are incl uded in practical combinational circuits. The redundant fault does not affect the functional behavior of the circuit even if it exists. The redundant fault, however, causes undesirable effects to the circuit su ch as increase of delay time and decrease of testability of the circui t. It is considered that some redundant faults may cause the logical d efects in the future. In this paper, firstly, we study the testability of the redundant fault in the combinational circuit by using delay ef fects. Secondly, we propose a method for generating a test-pair of a r edundant fault by using an extended seven-valued calculus, called TGRF (Test-pair Generation for Redundant Fault). TGRF generates a dynamica lly sensitizable path for the target line which propagates the change in the value on the target line to a primary output. Finally, we show experimental results on the benchmark circuits under the assumptions o f the unit delay and the fanout weighted delay models. It shows that t est-pairs for some redundant faults are generated theoretically.