BIST CIRCUIT MACRO USING MICROPROGRAM ROM FOR LSI MEMORIES

We developed an on-chip memory tester macro using 3 microprogram ROM B IST circuit. Only slight modification of address buffers, data bus I/O circuits and control clock generators of the memory core circuits was required to implement this BIST macro. We fabricated a 1 Mb DRAM with the BIST, and experimental results showed that the measured shmoo plo t of VCC versus the cycle rime by the BIST closely agreed with that of a memory tester. Disagreement was caused by test address signal set-u p time delay and V-OH/V-OL differences in both test conditions. The BI ST macro will be especially useful for design-for-testability of embed ded memories.