USE OF A MONTE-CARLO WIRING YIELD SIMULATOR TO OPTIMIZE DESIGN OF RANDOM LOGIC-CIRCUITS FOR YIELD ENHANCEMENT

There is general trend toward larger chip size and tighter layout due to customer requests of loading more and more Functions on single chip . This trend makes yield difficult to be maintained high enough, since larger amount of defects are distributed on such large and tight-rule d chips. To overcome such a situation, RADLYS (RAnDom Logic Yield Simu lator) and DD-TEG (Defect Density TEG) have been developed. DD-TEG ext racts defect size distribution and its amount automatically, while RAD LYS simulates defects on any layout and outputs yield based on the ext racted defect size distribution. Critical layout from yield point of v iew can be found in this procedure. DD-TEG and RADLYS are used as a se t of parameter extraction and simulation of the SPICE. In this paper, we introduce these tools and showed two application results. The predi cted yield showed a good agreement with the actual yield in the first application (Optical Device A). Critical layout at the Local I/O porti on was found in the second application (Random Logic portion of Memory Device B) and the layout was changed based on the RADLYS results.