FULLY SELF-TIMING DATA-BUS ARCHITECTURE FOR 64-MB DRAMS

This paper proposes a fully self-timing data-bus (FSD) architecture wh ich includes a dual data-bus driven by the read-out data itself and a complementary output differential (COD) amplifier. The proposed COD am plifier achieves a high voltage gain and a high speed data transfer wi th low power consumption. The read-out data is transmitted from the CO D amplifier to the output terminal without the timing control caused b y the fluctuation of the device parameters. Therefore the proposed FSD architecture eliminates the timing delay and achieves a timing-free d ata transfer even in DRAMs ls with a small signal level at the sense a mplifier and the data line. Applying this architecture to a 64-Mb DRAM , a fast column address access time of 16 ns and a RAS access time of 32 ns have been achieved.